`include "define.sv"
 
module apb_master (
    input  wire         PCLK,
    input  wire         PRESETn,
    output reg  [31:0]  PADDR,
    output reg          PWRITE,
    output reg  [31:0]  PWDATA,
    output reg          PENABLE,
    output reg          PSEL,
    input  wire [31:0]  PRDATA,
    input  wire         PREADY,
    input  wire         PSLVERR
);

    typedef enum logic [1:0] { IDLE, SETUP, ACCESS } state_t;
    state_t state;

    reg [1:0] matrix_type = `m32n8k16;
    reg [1:0] data_type   = `INT8;

    always @(posedge PCLK or negedge PRESETn) begin
        if (!PRESETn) begin
            state    <= IDLE; 
            PADDR    <= 32'h0;
            PWRITE   <= 1'b0;
            PWDATA   <= 32'h0;
            PENABLE  <= 1'b0;
            PSEL     <= 1'b0;
        end else begin
            case (state)
                IDLE: begin
                    PSEL    <= 1'b1;
                    PWRITE  <= 1'b1;
                    PADDR   <= 32'h0000_0004;
                    PWDATA  <= {matrix_type, data_type};
                    state   <= SETUP;
                end
                SETUP: begin
                    PENABLE <= 1'b1;
                    state   <= ACCESS;
                end
                ACCESS: begin
                    if (PREADY) begin
                        PENABLE <= 1'b0;
                        PSEL    <= 1'b0;
                        state   <= IDLE;
                    end
                end
            endcase
        end
    end
endmodule